Capabilities testing on 5.8.x


Advanced search

Message boards : Number crunching : Capabilities testing on 5.8.x

Sort
Author Message
Profile Andre Kerstens
Forum moderator
Project tester
Volunteer tester
Avatar

Joined: Sep 11 06
Posts: 749
ID: 1
Credit: 15,199
RAC: 0
Message 2276 - Posted 20 Jan 2007 19:56:17 UTC

I've posted the celeron problem we have on the boinc_dev list and Rom Walton came back with a reply that needs some testing:


Andre,

My gut tells me this might be a difference between Celeron's
with and without an FPU.

Could you get some volunteers with Celeron processors to run 5.8
on Windows and report back what there p_capabilities block looks like in client_state.xml?

It should look something like this:
<p_capabilities>fpu tsc sse sse2 mmx</p_capabilities>

If I'm right, the 'fpu' flag will be missing from the older
generation of Celeron processors, and so the OS falls back to software emulation to do the calculations.

----- Rom


Anyone with a Celeron cpu care to test this out? We need at least one pre-P4 and one P4 or later Celeron.

Thanks
Andre
____________
D@H the greatest project in the world... a while from now!
(retired account)
Volunteer tester

Joined: Nov 22 06
Posts: 62
ID: 331
Credit: 158,686
RAC: 0
Message 2277 - Posted 20 Jan 2007 20:39:37 UTC - in response to Message ID 2276 .
Last modified: 20 Jan 2007 20:43:36 UTC


[quote]
Andre,

My gut tells me this might be a difference between Celeron's
with and without an FPU.

Could you get some volunteers with Celeron processors to run 5.8
on Windows and report back what there p_capabilities block looks like in client_state.xml?

It should look something like this:
<p_capabilities>fpu tsc sse sse2 mmx</p_capabilities>

If I'm right, the 'fpu' flag will be missing from the older
generation of Celeron processors, and so the OS falls back to software emulation to do the calculations.

----- Rom


Hmm... I don't want to appear as a smart a.., but the last x86 cpu without FPU (floating-point unit) was the 486SX, so they should all have the 'fpu tsc' flags. tsc should be the time stamp counter.

But maybe the sse2 flag might help here. SSE2 should only be supported by Celeron based on the Pentium 4 or the Pentium M core. The Pentium III Celeron should support SSE (I'm not sure if all do) and the Pentium II Celeron should only support MMX.

I try to revive my 'Mendocino' Celeron...

Regards

Alex

P.S.: I didn't knew that the version 5.8.x has these capabilities, quite cool.
____________
Profile clownius
Volunteer tester
Avatar

Joined: Nov 14 06
Posts: 61
ID: 280
Credit: 2,677
RAC: 0
Message 2279 - Posted 20 Jan 2007 23:25:05 UTC

I have a 700 Mhz celeron coppermine and a 2Ghz celeron (im guessing its p4 based) but im on Linux does that help anyway?
____________

(retired account)
Volunteer tester

Joined: Nov 22 06
Posts: 62
ID: 331
Credit: 158,686
RAC: 0
Message 2284 - Posted 21 Jan 2007 1:05:29 UTC

Windows

Computer ID 1376 : Intel Celeron 'Mendocino' (Pentium II class)


<p_vendor>GenuineIntel</p_vendor>
<p_model>x86 Family 6 Model 6 Stepping 5 467MHz</p_model>
<p_capabilities>fpu tsc mmx</p_capabilities>


Computer ID 1017 : Intel Pentium III 'Coppermine'

<p_vendor>GenuineIntel</p_vendor>
<p_model>x86 Family 6 Model 8 Stepping 6 1002MHz</p_model>
<p_capabilities>fpu tsc sse mmx</p_capabilities>


Computer ID 1315 : Cyrix MII / IBM 6x86MX 'M2'

<p_vendor>CyrixInstead</p_vendor>
<p_model>x86 Family 6 Model 0 Stepping 0 250MHz</p_model>
<p_capabilities>fpu tsc mmx</p_capabilities>


Computer ID 1007 : AMD Athlon 64 'Clawhammer' (K8)

<p_vendor>AuthenticAMD</p_vendor>
<p_model>AMD Athlon(tm) 64 Processor 3200+</p_model>
<p_capabilities>fpu tsc pae nx sse sse2 3dnow mmx</p_capabilities>


Computer ID 1087 : AMD Athlon XP 'Thoroughbred' (K7)

<p_vendor>AuthenticAMD</p_vendor>
<p_model>AMD Athlon(tm) XP 2400+</p_model>
<p_capabilities>fpu tsc sse 3dnow mmx</p_capabilities>


Linux is a little bit more verbose...

Computer ID 1377 : Pentium II 'Deschutes'

<p_vendor>GenuineIntel</p_vendor>
<p_model>Pentium II (Deschutes)</p_model>
<p_capabilities>fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat pse36 mmx fxsr</p_capabilities>


Computer ID 1004 : AMD Athlon XP 'Thoroughbred' (K7)

<p_vendor>AuthenticAMD</p_vendor>
<p_model>AMD Athlon(tm) MP 2400+</p_model>
<p_capabilities>fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 mmx fxsr sse syscall mp mmxext 3dnowext 3dnow ts</p_capabilities>
Profile clownius
Volunteer tester
Avatar

Joined: Nov 14 06
Posts: 61
ID: 280
Credit: 2,677
RAC: 0
Message 2286 - Posted 21 Jan 2007 8:06:47 UTC

Linux tells you everything already so i guess that doesn't help. I wont be installing windoze on my lovely Linux boxes for anyone.
____________

Memo
Forum moderator
Project developer
Project tester

Joined: Sep 13 06
Posts: 88
ID: 14
Credit: 1,666,392
RAC: 0
Message 2288 - Posted 21 Jan 2007 17:01:41 UTC

well by the look of this we can discard the absence of FPU in celerons. I belive that the netburst architecture is where we see different results.
I don't remember if the last generation of P3s and the first of P4 have the same implementation of the SSE instructions probably Alexander can tells us a little bit about us.

Profile David Ball
Forum moderator
Volunteer tester
Avatar

Joined: Sep 18 06
Posts: 274
ID: 115
Credit: 1,634,401
RAC: 0
Message 2296 - Posted 22 Jan 2007 4:02:01 UTC - in response to Message ID 2288 .
Last modified: 22 Jan 2007 4:26:32 UTC

well by the look of this we can discard the absence of FPU in celerons. I belive that the netburst architecture is where we see different results.
I don't remember if the last generation of P3s and the first of P4 have the same implementation of the SSE instructions probably Alexander can tells us a little bit about us.


They've stopped updating the site, but if you're looking for info on chips from late 2004 and earlier, check out This Site .

Another excellent site for processor info is Sandpile.org

HTH,

____________
The views expressed are my own.
Facts are subject to memory error :-)
Have you read a good science fiction novel lately?
(retired account)
Volunteer tester

Joined: Nov 22 06
Posts: 62
ID: 331
Credit: 158,686
RAC: 0
Message 2297 - Posted 22 Jan 2007 9:56:01 UTC - in response to Message ID 2279 .
Last modified: 22 Jan 2007 9:56:14 UTC

I have a 700 Mhz celeron coppermine and a 2Ghz celeron (im guessing its p4 based) but im on Linux does that help anyway?


IMHO, it would help indeed. We could check for the existence or absence of the SSE and SSE2 flags (and assume they would also appear on Windows... ;-) ).

Regards

Alex
(retired account)
Volunteer tester

Joined: Nov 22 06
Posts: 62
ID: 331
Credit: 158,686
RAC: 0
Message 2300 - Posted 22 Jan 2007 10:47:37 UTC - in response to Message ID 2296 .
Last modified: 22 Jan 2007 10:49:32 UTC


Another excellent site for processor info is Sandpile.org


Yep, I concur. :-) I can also recommend Chris Hare's site. Even though it is a 'private' webpage, I found it to have very reliable information:

786-class cpus
586- and 686- class cpus

I have checked the Celeron datasheets available at Intel's site here and here and I'd say we can safely assume that all Pentium 4 or Pentium M based Celerons have the SSE2 instruction set while all older Celerons (based on Pentium III or Pentium II) do not have SSE2. So based on the absence or existence of the 'sse2' flag within the <p_capabilities> tags in the host information, it should be possible to discriminate between pre-P4 and P4/post-P4 Celerons. Of course, this would require everyone to use the 5.8.x series of BOINC, but I guess, this series will soon become the official client anyway.

Last but not least a table of the different Celeron breeds and the instruction sets they support:


  • Celeron 'Covington', PII-class, slot 1, ~ 266 - 300 MHz
  • supports MMX
  • Celeron 'Mendocino', PII-class, slot 1 & socket 370, ~ 300 - 533 MHz
  • supports MMX
  • Celeron 'Coppermine', PIII-class, socket 370, ~ 533 MHz - 1.1 GHz
  • supports MMX, SSE
  • Celeron 'Tualatin', PIII-class, socket 370, ~ 0.9 - 1.4 GHz
  • supports MMX, SSE
  • Celeron 'Willamette', P4-class, socket 478, ~ 1.7 - 1.8 GHz
  • supports MMX, SSE, SSE2
  • Celeron 'Northwood', P4-class, socket 478, ~ 1.6 - 2.8 GHz
  • supports MMX, SSE, SSE2
  • Celeron M 'Banias?', Pentium M-class, mobile comp., ~ 0.8 - 1.7 GHz
  • supports MMX, SSE, SSE2
  • Celeron D 'Prescott', P4-class, socket 478 & 775, ~ 2.1 - 3.3 GHz
  • supports MMX, SSE, SSE2, SSE3



Well, I hope Intel does not introduce a Core 2-based Celeron, the above is already confusing enough. :-)

Regards

Alex
____________

(retired account)
Volunteer tester

Joined: Nov 22 06
Posts: 62
ID: 331
Credit: 158,686
RAC: 0
Message 2301 - Posted 22 Jan 2007 12:34:04 UTC - in response to Message ID 2300 .
Last modified: 22 Jan 2007 12:34:29 UTC

I should add some of the newest Celeron D and Celeron M, to make this table really complete (hopefully). Unfortunately I'm too late to edit.


  • Celeron 'Covington', PII-class, slot 1, ~ 266 - 300 MHz
  • supports MMX
  • Celeron 'Mendocino', PII-class, slot 1 & socket 370, ~ 300 - 533 MHz
  • supports MMX
  • Celeron 'Coppermine', PIII-class, socket 370, ~ 533 MHz - 1.1 GHz
  • supports MMX, SSE
  • Celeron 'Tualatin', PIII-class, socket 370, ~ 0.9 - 1.4 GHz
  • supports MMX, SSE
  • Celeron 'Willamette', P4-class, socket 478, ~ 1.7 - 1.8 GHz
  • supports MMX, SSE, SSE2
  • Celeron 'Northwood', P4-class, socket 478, ~ 1.6 - 2.8 GHz
  • supports MMX, SSE, SSE2
  • Celeron M 'Banias' or 'Dothan', Pentium M-class, mobile comp., ~ 0.8 - 1.7 GHz
  • supports MMX, SSE, SSE2
  • Celeron M 'Yonah', Core-class, mobile comp., ~ 1.0 - 2.0 GHz
  • supports MMX, SSE, SSE2, SSE3
  • Celeron D 'Prescott', P4-class, socket 478 & 775, ~ 2.1 - 3.3 GHz
  • supports MMX, SSE, SSE2, SSE3
  • Celeron D 'Cedar Mill', P4-class, socket 775, ~ 3.0 - 3.5 GHz
  • supports MMX, SSE, SSE2, SSE3



... phew! :-)

Regards

Alex

coldshot
Volunteer tester

Joined: Nov 14 06
Posts: 7
ID: 306
Credit: 93,007
RAC: 0
Message 2305 - Posted 22 Jan 2007 19:12:54 UTC
Last modified: 22 Jan 2007 19:14:43 UTC

Good morning Alexander,

CID 1374 Processor x86 Family 6 Model 11 Stepping 1 GenuineIntel ~1196 Mhz


I know this is more than you asked for but, I don't know, it might be helpful.

<p_ncpus>1</p_ncpus>
<p_vendor>GenuineIntel</p_vendor>
<p_model>Intel(R) Celeron(TM) CPU 1200MHz</p_model>
<p_capabilities>fpu tsc sse mmx</p_capabilities>
<p_fpops>1037037037.037037</p_fpops>
<p_iops>1902681328.117460</p_iops>
<p_membw>1000000000.000000</p_membw>
<p_calculated>1169293311.250000</p_calculated>
<m_nbytes>401063936.000000</m_nbytes>
<m_cache>1000000.000000</m_cache>
<m_swap>966000640.000000</m_swap>
<d_total>40007368704.000000</d_total>
<d_free>37612421120.000000</d_free>
<os_name>Microsoft Windows XP</os_name>
<os_version>Professional Edition, Service Pack 2, (05.01.2600.00)</os_version>
<accelerators>Intel(R) 82810E Graphics Controller (Microsoft Corporation)</accelerators>

Thanks
Cold Shot

Profile David Ball
Forum moderator
Volunteer tester
Avatar

Joined: Sep 18 06
Posts: 274
ID: 115
Credit: 1,634,401
RAC: 0
Message 2308 - Posted 23 Jan 2007 12:03:02 UTC

Machine 1253 - The machine that will not run D@H even with ulimit -s unlimited.
Linux RHEL3 - Celeron 2.4 GHz - BOINC client version 5.8.4 for i686-pc-linux-gnu

<p_vendor>GenuineIntel</p_vendor>
<p_model>Intel(R) Celeron(R) CPU 2.40GHz</p_model>
<p_capabilities>fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm</p_capabilities>
<p_fpops>914634146.341463</p_fpops>
<p_iops>1414682246.908896</p_iops>
<p_membw>1000000000.000000</p_membw>
<p_calculated>1169549011.850046</p_calculated>
<m_nbytes>2091413504.000000</m_nbytes>
<m_cache>131072.000000</m_cache>
<m_swap>2089177088.000000</m_swap>
<d_total>17196134400.000000</d_total>
<d_free>12347961344.000000</d_free>
<os_name>Linux</os_name>
<os_version>2.4.21-47.0.1.EL</os_version>
<accelerators></accelerators>

ulimit -a returns
core file size (blocks, -c) 0
data seg size (kbytes, -d) unlimited
file size (blocks, -f) unlimited
max locked memory (kbytes, -l) 4
max memory size (kbytes, -m) unlimited
open files (-n) 1024
pipe size (512 bytes, -p) 8
stack size (kbytes, -s) unlimited
cpu time (seconds, -t) unlimited
max user processes (-u) 7168
virtual memory (kbytes, -v) unlimited


I included some extra info, just in case someone gets an idea why this machine runs Rosetta, Einstein, and Seti just fine, but will NOT run docking.

It's been a very long time (probably 6 - 12 months) since I tried, but this machine wouldn't run CPDN either.

____________
The views expressed are my own.
Facts are subject to memory error :-)
Have you read a good science fiction novel lately?

Message boards : Number crunching : Capabilities testing on 5.8.x

Database Error
: The MySQL server is running with the --read-only option so it cannot execute this statement
array(3) {
  [0]=>
  array(7) {
    ["file"]=>
    string(47) "/boinc/projects/docking/html_v2/inc/db_conn.inc"
    ["line"]=>
    int(97)
    ["function"]=>
    string(8) "do_query"
    ["class"]=>
    string(6) "DbConn"
    ["object"]=>
    object(DbConn)#17 (2) {
      ["db_conn"]=>
      resource(84) of type (mysql link persistent)
      ["db_name"]=>
      string(7) "docking"
    }
    ["type"]=>
    string(2) "->"
    ["args"]=>
    array(1) {
      [0]=>
      &string(51) "update DBNAME.thread set views=views+1 where id=164"
    }
  }
  [1]=>
  array(7) {
    ["file"]=>
    string(48) "/boinc/projects/docking/html_v2/inc/forum_db.inc"
    ["line"]=>
    int(60)
    ["function"]=>
    string(6) "update"
    ["class"]=>
    string(6) "DbConn"
    ["object"]=>
    object(DbConn)#17 (2) {
      ["db_conn"]=>
      resource(84) of type (mysql link persistent)
      ["db_name"]=>
      string(7) "docking"
    }
    ["type"]=>
    string(2) "->"
    ["args"]=>
    array(3) {
      [0]=>
      object(BoincThread)#3 (16) {
        ["id"]=>
        string(3) "164"
        ["forum"]=>
        string(1) "2"
        ["owner"]=>
        string(1) "1"
        ["status"]=>
        string(1) "0"
        ["title"]=>
        string(29) "Capabilities testing on 5.8.x"
        ["timestamp"]=>
        string(10) "1169553782"
        ["views"]=>
        string(4) "1272"
        ["replies"]=>
        string(2) "11"
        ["activity"]=>
        string(22) "5.909831119928499e-125"
        ["sufferers"]=>
        string(1) "0"
        ["score"]=>
        string(1) "0"
        ["votes"]=>
        string(1) "0"
        ["create_time"]=>
        string(10) "1169322977"
        ["hidden"]=>
        string(1) "0"
        ["sticky"]=>
        string(1) "0"
        ["locked"]=>
        string(1) "0"
      }
      [1]=>
      &string(6) "thread"
      [2]=>
      &string(13) "views=views+1"
    }
  }
  [2]=>
  array(7) {
    ["file"]=>
    string(63) "/boinc/projects/docking/html_v2/user/community/forum/thread.php"
    ["line"]=>
    int(184)
    ["function"]=>
    string(6) "update"
    ["class"]=>
    string(11) "BoincThread"
    ["object"]=>
    object(BoincThread)#3 (16) {
      ["id"]=>
      string(3) "164"
      ["forum"]=>
      string(1) "2"
      ["owner"]=>
      string(1) "1"
      ["status"]=>
      string(1) "0"
      ["title"]=>
      string(29) "Capabilities testing on 5.8.x"
      ["timestamp"]=>
      string(10) "1169553782"
      ["views"]=>
      string(4) "1272"
      ["replies"]=>
      string(2) "11"
      ["activity"]=>
      string(22) "5.909831119928499e-125"
      ["sufferers"]=>
      string(1) "0"
      ["score"]=>
      string(1) "0"
      ["votes"]=>
      string(1) "0"
      ["create_time"]=>
      string(10) "1169322977"
      ["hidden"]=>
      string(1) "0"
      ["sticky"]=>
      string(1) "0"
      ["locked"]=>
      string(1) "0"
    }
    ["type"]=>
    string(2) "->"
    ["args"]=>
    array(1) {
      [0]=>
      &string(13) "views=views+1"
    }
  }
}
query: update docking.thread set views=views+1 where id=164